1. Field of the Invention
The present invention relates to a code division multiple access (hereinafter referred to as CDMA) demodulating method and demodulator, and more particularly, to a CDMA demodulating method and demodulator, in which the architectural complexity of hardware is reduced so that various services may be provided only by software download.
2. Description of the Related Art
In general, in a CDMA receiver, which receives a CDMA signal after it has passed through a wireless channel, signal components having different delays and amplitudes are added to the CDMA signal. According to conventional CDMA demodulating methods, PN codes and walsh codes are generated and multiplied with a received CDMA signal. Next, weighting values are given to signals after they have been multiplied by the PN codes, the weighted signals are phase adjusted, and the resultant signals are summed.
FIG. 1 illustrates a block diagram of the structure of a conventional CDMA demodulator. Referring to FIG. 1, the conventional CDMA demodulator includes as many fingers as the number of multi-paths to be considered and thereby processes the received CDMA signal by generating PN codes and traffic walsh codes, which vary according to the degree of delay of each path.
However, in the conventional CDMA receiver, a number (N) of PN-codes generators and traffic walsh codes-generators must operate simultaneously and consecutively with respect to a number (N) of the multi-paths. However, since the traffic walsh codes-generator operates when the traffic walsh codes of only one period are generated, it is necessary to reduce the architectural complexity of the hardware and the power consumption.
It is feature of the present invention to provide a CDMA demodulating method having a suitable architecture for implementation on a processor so that the architectural complexity of hardware can be reduced and various services can be provided only by software download.
Another feature of the present invention is to provide a CDMA demodulator using the CDMA demodulating method.
These and other features of the present invention may be achieved according to one aspect of the present invention, wherein there is provided a CDMA demodulating method. The CDMA demodulating method comprises the steps of (a) sequentially-storing all input data, which are over-sampled by M-fold and go through a number (N) of paths, in a predetermined first memory, where M and N are predetermined positive integers; (b) generating PN codes for each of the N paths and storing the PN codes in a predetermined second memory; (c) generating and sequentially-storing traffic walsh codes of one period, which correspond to a processing gain L, in a predetermined third memory; (d) multiplying a complex-conjugated value with one of the values stored in the first memory and one of the values stored in the second memory; (e) performing a control operation for storing the PN codes in a predetermined address of the second memory and a control operation for outputting data for each of the N paths from the first, second, and third memories; (f) multiplying the resultant value of the step (d) with the traffic walsh codes of a corresponding path of data stored in the third memory; (g) cumulatively summing the resultant value of the step (f) L times for each of the N multi-paths to be processed, where L corresponds to the processing gain; (h) complex-conjugating the resultant value of the step (d) by cumulatively adding the resultant value of the step (d) X times for each of the N multi-paths to be processed, where X corresponds to the data bit number of the walsh codes; (i) obtaining a number (N) of data by inputting the resultant value of the step (f) and the resultant value of the step (h) and multiplying the resultant value of the step (f) with the resultant value of the step (h); (j) sequentially-obtaining a number (N) of values by sequentially-inputting the number (N) of data obtained in the step (i) and taking only real values; (k) cumulatively summing the data obtained in step (i) N times; and (l) deciding bit values based on logic values identified by identifying the logic values of the result of the step (k).
In accordance with another aspect of the present invention, there is provided another CDMA demodulating method. This CDMA demodulating method comprises the steps of: (a) sequentially-storing all input data, which are over-sampled by M-fold and go through a number (N) of paths, in a predetermined first memory, where M and N are predetermined positive integers; (b) generating PN codes for each of the N paths; (c) storing the PN codes in a predetermined second memory; (d) complex-conjugating the PN codes; (e) checking whether traffic walsh codes of all one period are stored in a predetermined third memory; (f) sequentially-storing the traffic walsh codes by generating the traffic walsh codes, which correspond to a first access path, until traffic walsh codes of all one period, which corresponds to a processing gain L, are stored in a case where traffic walsh codes of all one period are not stored in the third memory; (g) omitting the performance of step (f) in a case where traffic walsh codes of all one period are stored in the third memory; (h) multiplying a complex-conjugated value with one of the values stored in the first memory and one of the values stored in the second memory; (i) performing a control operation for storing the PN codes in a predetermined address of the second memory and a control operation for outputting data for each of the N paths from the first, second, and third memories; (j) multiplying the resultant value of the step (h) with the traffic walsh codes of a corresponding path of data stored in the third memory; (k) cumulatively summing the resultant value of step (j) L times for each of the N multi-paths to be processed, where L corresponds to the processing gain; (l) cumulatively summing the resultant value of step (h) X times for each of the N multi-paths to be processed, where X corresponds to the data bit number of the walsh codes; (m) checking whether L-1 resultant values are accumulated; (n) checking whether N resultant values are accumulated when it is determined that the L-1 resultant values are not accumulated in the step (m); (o) repeatedly-performing steps (j) through (n) with respect to the values by outputting the values, which correspond to a next path in the first, second, third memories, when it is determined that the N resultant values are not accumulated in step (n); (p) performing steps (a) through (o) when it is determined that work with respect to the N-th path is completed in step (n); (q) performing steps (a) through (l) when it is determined that the L-1 resultant values are accumulated in step (m); (r) multiplying the complex-conjugated value of the resultant value of step (l) with the resultant value of step (k); (s) sequentially-obtaining a number (N) of values by sequentially-inputting the number (N) of data obtained in step (r) and taking only real values; (t) cumulatively summing the data obtained in step (s) N times; and (u) deciding bit values based on logic values identified by identifying the logic values of the result of step (t).
In another aspect of the present invention, there is provided a CDMA demodulator in which the above CDMA demodulating method is implemented. The CDMA demodulator comprises: a first memory for sequentially-storing input data, which are over-sampled by M-fold, where M is a predetermined positive integer; a PN codes-generating unit for generating different PN codes for each path; a second memory for sequentially-storing the PN codes output from the PN codes-generating unit; a first complex-conjugating unit for complex-conjugating the PN codes by inputting from the second memory the PN codes generated by the PN codes-generating unit; a first multiplying unit for multiplying a complex-conjugated value of one of the values stored in the second memory with one of the values stored in the first memory; a controlling unit for performing a control operation for storing the PN codes generated in the PN codes-generating unit in the same address as the modulo K-operated result, in the order in which the PN codes are received from the second memory and for performing a control operation for outputting data for each path from the first, second, and third memories; a second multiplying unit for multiplying a value output from the first multiplying unit with traffic walsh codes of a corresponding path of data stored in the third memory; an N-path L-accumulating unit for cumulatively-summing the output data of the second multiplying unit L times for each of the N paths to be processed, where L corresponds to the processing gain; an N-path X-accumulating unit for cumulatively-summing the data output from the first multiplying unit X times for each of the N multi-paths to be processed, where X corresponds to the data bit number of the walsh codes; a second complex-conjugating unit for complex-conjugating the output values of the N-path X-accumulating unit by inputting the output values of the N-path X-accumulating unit; a third multiplying unit for multiplying the output values of the second complex-conjugating unit with the output values of the N-path L-accumulating unit; a real-values extracting unit for sequentially and for each path independently inputting N data values output from the third multiplying unit, and for sequentially-outputting the N independent values for each path, and taking only real values; an accumulating unit for cumulatively-summing the data sequentially-output from the real-values extracting unit N times; and a bit-deciding unit for deciding bit values based on logic values identified by identifying the logic values of the output of the accumulating unit.